1. Field of the Invention
The present invention relates to a flat panel display and, more particularly, to a full color active matrix organic light emitting display (AMOLED), which lowers taper angles of an anode and a via hole to prevent defects from occurring.
2. Description of the Related Art
In general, AMOLED has a plurality of pixels arranged on a substrate in a matrix format, and each pixel includes an electroluminescent (EL) element with an anode, an organic emission layer, and a cathode that are layered together. The AMOLED also includes a thin film transistor (TFT) connected to the EL element as an active element for driving the EL element.
FIG. 1 is a cross-sectional view of a bottom-emitting organic light emitting display (OLED) in accordance with the prior art. Referring to FIG. 1, a buffer layer 105 is formed on an insulating substrate 100, and a semiconductor layer 110 having source and drain regions 111 and 115 is formed on the buffer layer 105. A gate electrode 125 is formed on a gate insulating layer 120, and source and drain electrodes 141 and 145 are formed on an interlayer insulating layer 130, and are connected to the source and drain regions 111 and 115 through contact holes 131 and 135, respectively. This way, the TFT is fabricated.
An anode 170 as a lower electrode is formed on a passivation layer 150, and is connected through a via hole 155 to the drain electrode 145 of the source and drain electrodes 141 and 145. An organic emission layer 185 and a cathode 190 as an upper electrode are formed on the substrate. In this manner, the organic EL element is fabricated.
In the conventional organic light emitting display having the above-mentioned structure, when taper angles θ11 and θ12 of the contact holes or via hole are large, pin hole defects have occurred at stepped portions of the anode 170 and near the contact hole or via hole, or open circuit defects between the anode and the cathode have occurred. In addition, the organic emission layer has not been deposited on the stepped portions of the anode and near the contact hole and via hole, or it has not been uniformly deposited to thereby have a thickness thinner than those of other portions. Thus, when a high voltage is applied between the anode and the cathode, the portion where the organic emission layer is not deposited or thinly deposited has current density concentrated to generate circular dark spots. Due to the occurrence of the dark spots, emission regions become reduced to thereby deteriorate image quality.
In addition, the cathode to be deposited over the entire surface of the substrate is not densely formed in the stepped portion, which causes external oxygen or moisture to penetrate through the portion that is not densely formed. Thus, when a high voltage is applied between the anode and the cathode, the portion that is not densely deposited has a void in the cathode due to electromigration resulting from the current density concentration, so that high heat occurs due to a resistance increase resulting from external oxygen penetration. As a result, the portion has circular dark spots generated as time proceeds.
FIG. 4 is a cross-sectional photograph near a contact hole for indicating the deterioration mechanism resulting from a high taper angle of the contact hole or via hole in the conventional OLED. Referring to FIG. 4, oxygen or moisture penetrates through the open portion of the cathode 190 resulting from pin hole defects near the contact hole or via hole, so that the deterioration may be diffused.
FIG. 5 is a graph for explaining a relationship between the number of defects and taper angles of a contact hole or via hole in the conventional OLED. Referring to FIG. 5, it can be seen that the defects near the contact hole or via hole may be prevented when the taper angle of the contact hole or via hole is 60° or less. FIG. 6 is a photograph that shows occurrences of dark spots at the edge portion of the emission region when the taper angle of the contact hole or via hole is large. Referring to FIG. 6, it can be seen that a lot of dark spots generate near the edge portion of the emission region when the taper angle of the contact hole or via hole is 75°. In this case, the reference numerals 61 and 62 indicate dark spots occurred near via hole and the contact hole, respectively.
U.S. Pat. No. 5,684,365 discloses a technique, which limits a taper angle of a passivation layer at an edge of an opening for exposing some portions of an anode. FIG. 2 is a cross-sectional view of the conventional bottom-emitting OLED. Referring to FIG. 2, a buffer layer 205 is formed on an insulating substrate 200, and a semiconductor layer 210 having source and drain regions 211 and 215 is formed on the buffer layer 205. A gate electrode 225 is formed on a gate insulating layer 220, and source and drain electrodes 241 and 245 are formed on an interlayer insulating layer 230, and are connected to the source and drain regions 211 and 215 through contact holes 231 and 235, respectively. Further, an anode 270 as a lower electrode is formed on the interlayer insulating layer 230, and is connected to the drain electrode 245.
A passivation layer 250 formed of an insulating layer such as a silicon nitride layer is deposited to have a 0.5 to 1.0 μm in thickness on the substrate, and is etched to form an opening 275 for exposing some portions of the anode 270. In this case, the passivation layer 250 is arranged at the edge of the opening 275 to have a taper angle θ21 of 10° to 30° with respect to the anode 270. An organic emission layer 285 and a cathode 290 as an upper electrode are then formed on the substrate.
In the conventional flat panel display having the above-mentioned structure, the taper angle θ21 of the passivation layer contacted with the anode is limited to be in a range of 10° to 30° when the passivation is etched to expose some portions of the anode so as to prevent defects of the organic emission layer from occurring. However, pin hole or open circuit defects still generate near the contact hole, the via hole, or in the stepped portion as shown in FIG. 4 and FIG. 5, and dark spots are also generated due to the cathode that is not densely deposited.
In addition, U.S. Pat. No. 6,246,179 discloses a technique employing an organic insulating layer with planarizing property to prevent defects from occurring near the via hole, contact hole, or in the stepped portion. FIG. 3 is a cross-sectional view of the OLED having the conventional top-emitting structure. Referring to FIG. 3, a buffer layer 305 is formed on an insulating layer 300, and a semiconductor layer 310 having source and drain regions 311 and 315 is formed on the buffer layer 305. A gate electrode 325 is formed on a gate insulating layer 320, and source and drain electrodes 341 and 345 are formed on the interlayer insulating layer 330, and are connected to the source and drain regions 311 and 315 through contact holes 331 and 335, respectively.
A planarizing layer 360 is formed on a passivation 350, and an anode 370 as a lower electrode is formed on the planarizing layer 360, and is connected through a via hole 355 to one of the source and drain electrodes 341 and 345, for example, to the drain electrode 345. A pixel defining layer 365 is then formed to have an opening 375 for exposing some portions of the anode 370, and an organic emission layer 385 and a cathode 390 as an upper electrode are formed on the anode 370 and the pixel defining layer 365.
In the above-mentioned OLED, a taper angle θ31 of the pixel defining layer is limited in a range of 20° to 80° to prevent defects of the organic emission layer, and the planarizing layer is used for preventing element defects from occurring near the contact hole or via hole due to the stepped portion of the substrate surface. However, reliability of the element is dependent on the taper angle between the pixel defining layer and the anode. By way of example, the organic emission layer and the cathode are likely to be deteriorated at the edge of the opening when the taper angle is large, and there is a limit to reducing the taper angle and the thickness of the pixel defining layer because of a parasitic capacitance and a step resulting from wiring when the taper angle is small.
Further, an aperture ratio is further decreased with the increasing use of the pixel defining layer, and outgas from the pixel defining layer causes the emission region to be reduced, which leads to pixel size reduction, so that lifetime and image quality are deteriorated, and additional processes for depositing and etching the pixel defining layer are required.